1. Field of the Invention
The present invention relates to an output circuit and, particularly, to an output circuit of an integrated circuit which has an output terminal applied with a voltage higher than a source voltage thereof and is operable at a low voltage.
2. Description of Prior Art
Responsive to shortened gate length of MOS transistors caused by increase of integrating density and increase of operating speed of an integrated circuit (LSI) composed of CMOS circuits or BiCMOS circuits, an operating source voltage thereof is being reduced. Under such circumstances, when such an LSI operable at low voltage is combined with an LSI operable at the usual voltage, an interface is required between the LSI having mutually different source voltages. When an LSI having a source voltage is connected to another LSI having a different source voltage and an output terminal of an output circuit of the LSI having the lower operating voltage is imparted with a potential higher than its source voltage, the output circuit includes an over-voltage protection circuit for preventing current from flowing from the side of the high potential LSI to the lower potential LSI to restrict variations of the source voltage and current of the lower potential LSI.
Referring to FIG. 4 which is a circuit diagram of a conventional output circuit, the conventional output circuit includes inverters 1 and 2 having inputs connected to an input terminal TI, an output buffer circuit 4 which is adapted to be driven by these inverters 1 and 2 and output an output signal in response to output signal from the inverters 1 and 2 at an output terminal TO and a protection circuit 7 which is adapted to cut off the output transistor P1 when an over-voltage is applied to the output terminal TO to thereby prevent current from flowing thereinto.
The output buffer circuit 4 includes a PMOS transistor P1 having a source connected to a power source VDD, a gate connected to an output of the inverter 1 and a drain connected to the output terminal TO and an NMOS transistor N6 having a source grounded to GND, a gate connected to an output terminal of the inverter 2 and a drain connected to the output terminal TO.
The protection circuit 7 has a terminal a connected to the output of the inverter 1, a terminal b connected to a power source VDD, a terminal c connected to a well of the transistor P1, a terminal d connected to the input terminal TI and a terminal e connected to the output terminal TO. The protection circuit 7 includes a PMOS type transistor P15 having a source connected to the output of the inverter 1 through the terminal a, a gate connected to the power source VDD through the terminal b and a drain connected to the terminal e, a PMOS type transistor P16 having a source connected to the terminal b, a gate connected to the output terminal TO through the terminal e and a drain and an well connected each other and further connected to the wells of the transistors P1 and P15 through the terminal c, respectively, and a PMOS type transistor P17 having a source connected to the output of the inverter 1 through the terminal a, a gate connected to the input terminal TI through the terminal d and a drain and an well connected each other and further connected to the well of the transistor P16.
Now, an operation of the output circuit shown in FIG. 4 from which the protection circuit 7 is removed will be described. Assuming that the transistor P1 of the output circuit 4 is in ON state and the transistor N6 of the same is in OFF state, a potential of the output terminal TO is equal to that of the power source VDD. When, in this state, a high potential (referred to as "VPP", hereinafter, for simplicity of description) higher than the power source potential VDD is applied to the output terminal TO, a current path is formed from the output terminal TO through the transistor P1 to the power source VDD, causing a potential variation and/or current variation of the power source VDD to be induced. Further, it is well known that, when a well potential of the PMOS type transistor is lower than its source potential, not only a threshold value of the transistor varies but also a current path is formed from the source to a substrate, which cause the transistor itself to be degraded and cause a power consumption of a circuit including the transistor. Therefore, the well potential must be substantially the same as the source potential.
The protection circuit 7 is provided to prevent the current path described above from being formed. When the potential VPP is supplied to the terminal TO while To is outputting the potential VDD, the transistor P15 turns on because the source potential thereof becomes higher than a gate potential thereof. Therefore, the potential VPP supplied to the terminal TO is propagated to the gate electrode of the transistor P1 through the transistor P15 to thereby cut off the transistor P1. The transistor P17 is provided to make the well potentials of P1 and P15 to equal to the corresponding source potentials of P1 and P15, respectively to thereby prevent current flowing between the well region and the source region.
Further, the transistor P16 is provided to maintain the well potentials equal to the power source potential VDD when the output terminal TO is a ground potential GND.
When the output buffer outputs VDD level, the inverter outputs L level (ground level GND) to turn on P1. Therefore, a N-channel transistor of the inverter is in ON state. As a result, a current path from the terminal TO to the ground line through P15 and the N-channel transistor of the inverter is made.
Particularly, in the output circuit in a LSI which is operable at high speed, the output transistor having large channel width is used in the output buffer thereof. In order to drive such transistor having large channel width, the drive inverter is formed by using transistor having large channel width. Therefore, the current flowing from the output terminal TO to the ground GND becomes large, causing the problem of current consumption and heat generation to occur.